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Preliminary Technical Data
FEATURES
Polyphase Energy Metering IC with Pulsed Output ADE7752B
The no-load threshold and reverse polarity indication are based on the sum of the three phase energies in the ADE7752B. The ADE7752B specifications surpass the accuracy requirements as quoted in the IEC62053-21 standard. The only analog circuitry used in the ADE7752B is in the analog-to-digital converters (ADCs) and reference circuit. All other signal processing (for example, multiplication, filtering, and summation) is carried out in the digital domain. This approach provides superior stability and accuracy over extremes in environmental conditions and over time. The ADE7752B supplies average active power information on the low frequency outputs, F1 and F2. These logic outputs can be used to directly drive an electromechanical counter or to interface with an MCU. The CF logic output gives instantaneous active power information. This output is intended to be used for calibration purposes. The ADE7752B includes a power supply monitoring circuit on the VDD pin. The ADE7752B remains inactive until the supply voltage on VDD reaches 4 V. If the supply falls below 4 V, the ADE7752B also resets and no pulses are issued on F1, F2, and CF. Internal phase matching circuitry ensures that the voltage and current channels are phase matched. An internal no load threshold ensures the ADE7752B does not exhibit any creep when there is no load. The ADE7752B is available in a 24-lead SOIC package.
1
High accuracy supports 50 Hz/60 Hz IEC62053-21 Less than 0.1% error over a dynamic range of 500 to 1 Compatible with 3-phase 3-wire delta and 3-phase 4-wire Wye configurations Supplies average active power on the frequency outputs F1 and F2 High frequency output (CF) is intended for calibration and supplies instantaneous active power Logic output REVP indicates a potential miswiring or negative power on the sum of all phases Direct drive for electromechanical counters and 2-phase stepper motors (F1 and F2) Proprietary ADCs and DSP provide high accuracy over large variations in environmental conditions and time On-chip power supply monitoring On-chip creep protection (no load threshold) based on the sum of the three phases On-chip reference 2.4 V 8% (25 ppm/C typical) with external overdrive capability Single 5 V supply, low power (TBD mW typical) Low cost CMOS process
GENERAL DESCRIPTION
The ADE7752B1 is an accurate active energy measurement IC intended for use in any 3-phase distribution system and has enhanced features that make it better suited for 3-phase 3-wire applications compared to the ADE7752/52A.
Patent pending.
ABS
17
FUNCTIONAL BLOCK DIAGRAM
VDD
3
IAP 5 IAN 6 VAP
16
ADC HPF ADC PHASE CORRECTION LPF
X
POWER SUPPLY MONITOR
ADE7752B
X LPF
IBP IBN
7
ADC
8
HPF ADC PHASE CORRECTION
2 19 20
DGND CLKIN CLKOUT
VBP 15
ICP
9
ICN 10 VCP 14 VN 13 2.4V REF
11
ADC HPF ADC 4k
12
X LPF
DIGITAL-TO-FREQUENCY CONVERTER
05905-001
PHASE CORRECTION
4
18
21
22
23
24
1
AGND
REFIN/OUT
REVP
SCF
S0
S1
F2
F1
CF
Figure 1.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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ADE7752B TABLE OF CONTENTS
Features .............................................................................................. 1 General Description ......................................................................... 1 Table of Contents .............................................................................. 2 Specifications..................................................................................... 3 Timing Characteristics ................................................................ 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 9 Terminology .................................................................................... 11 Test Circuit ...................................................................................... 12 Theory of Operation ...................................................................... 13 Power Factor Considerations.................................................... 13 Nonsinusoidal Voltage and Current ........................................ 14 Analog Inputs.................................................................................. 15 Current Channels ....................................................................... 15 Voltage Channels ........................................................................ 15 Typical Connection Diagrams ...................................................... 16
Preliminary Technical Data
Current Channel Connection................................................... 16 Voltage Channels Connection .................................................. 16 Meter Connections..................................................................... 16 Power Supply Monitor ................................................................... 18 HPF and Offset Effects .................................................................. 19 Digital-to-Frequency Conversion ................................................ 20 Power Measurement Considerations....................................... 21 Mode Selection of the Sum of the Three Active Energies..... 21 Transfer Function ........................................................................... 22 Frequency Outputs F1 and F2 .................................................. 22 Frequency Output CF ................................................................ 23 Selecting a Frequency for an Energy Meter Application........... 24 Frequency Outputs..................................................................... 24 No Load Threshold .................................................................... 24 Negative Power Information..................................................... 25 Outline Dimensions ....................................................................... 26 Ordering Guide .......................................................................... 26
Rev. PrA | Page 2 of 27
Preliminary Technical Data SPECIFICATIONS
ADE7752B
VDD = 5 V 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz, TMIN to TMAX = -40C to +85C, unless otherwise noted. Table 1.
Parameter ACCURACY1, 2 Measurement Error on Current Channel Phase Error Between Channels PF = 0.8 Capacitive PF = 0.5 Capacitive AC Power Supply Rejection Output Frequency Variation (CF) DC Power Supply Rejection Output Frequency Variation (CF) ANALOG INPUTS Maximum Signal Levels Input Impedance (DC) Bandwidth (-3 dB) ADC Offset Error1, 2 Gain Error REFERENCE INPUT REFIN/OUT Input Voltage Range Input Impedance Input Capacitance ON-CHIP REFERENCE Reference Error Temperature Coefficient CLKIN Input Clock Frequency LOGIC INPUTS3 ACF, S0, S1, and ABS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN LOGIC OUTPUTS3 F1 and F2 Output High Voltage, VOH Output Low Voltage, VOL CF and NEGP Output High Voltage, VOH Output Low Voltage, VOL LED_CTRL Output Frequency Output High Voltage Output Low Voltage Conditions Voltage channel with full-scale signal (500 mV), 25C, over a dynamic range of 500 to 1 Min Typ 0.1 Max Unit % Reading
0.1 0.1 SCF = 0, S0 = S1 = 1 IA = IB = IC = 100 mV rms, VA = VB = VC = 100 mV rms @ 50 Hz, Ripple on VDD of 200 mV rms @ 100 Hz S1 = 1; S0 = SCF = 0 V1 = 100 mV rms, V2 = 100 mV rms, VDD = 5 V 250 mV See Analog Inputs section VAP - VN, VBP - VN, VCP - VN, IAP - IAN, IBP - IBN, ICP - ICN CLKIN = 10 MHz CLKIN/256, CLKIN = 10 MHz External 2.5 V reference, IA = IB = IC = 500 mV dc 2.4 V + 8% 2.4 V - 8% 2.2 3.3 10 Nominal 2.4 V 200 25 All specifications for CLKIN of 10 MHz 10 370 0.01
Degrees Degrees % Reading
0.1
% Reading
0.5 410 14 25 9 2.6
V peak difference k kHz mV % Ideal V V k pF mV ppm/C MHz
VDD = 5 V 5% VDD = 5 V 5% Typically 10 nA, VIN = 0 V to VDD
2.4 0.8 3 10
V V A pF
ISOURCE = 10 mA, VDD = 5 V ISINK = 10 mA, VDD = 5 V VDD = 5 V, ISOURCE = 5 mA VDD = 5 V, ISINK = 5 mA VDD = 5 V, CLKIN = 10 MHz VDD = 5 V, ISOURCE = 10 mA VDD = 5 V, ISINK = 10 mA
Rev. PrA | Page 3 of 27
4.5 0.5 4.5 0.5 17.39 4.5 TBD
V V V V kHz V V
ADE7752B
Parameter LED_A, LED_B, LED_C Output Low ISINK Output High Source POWER SUPPLY VDD IDD
1 2
Preliminary Technical Data
Conditions VDD = 4.75 V VDD = 4.75 V For specified performance 5 V 5% Min TBD TBD 4.75 TBD 5.25 TBD Typ Max Unit mA mA V mA
See the Terminology section for explanation of specifications. See the plots in the Typical Performance Characteristics section. 3 Sample tested during initial release and after any redesign or process changes that might affect this parameter.
Rev. PrA | Page 4 of 27
Preliminary Technical Data
TIMING CHARACTERISTICS
ADE7752B
VDD = 5 V 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz, TMIN to TMAX = -40C to +85C, unless otherwise noted. Table 2.
Parameter1,2 t1 3 t2 t3 t43, 4 t55 t6
1 2
Conditions F1 and F2 pulse width (logic high) Output pulse period (see the Transfer Function section) Time between F1 falling edge and F2 falling edge CF pulse width (logic high) CF pulse period (see the Transfer Function section) Minimum time between F1 and F2 pulse
Specification 120
See Figure 2 1/2 t2 90 See Table 7 4/CLKIN
Unit ms sec sec ms sec sec
Sample tested during initial release and after any redesign or process changes that might affect this parameter. See Figure 2. 3 The pulse widths of F1, F2, and CF are not fixed for higher output frequencies (see the Frequency Outputs section). 4 CF is not synchronous to F1 or F2 frequency outputs. 5 The CF pulse is always 1 s in the high frequency mode (see the Frequency Outputs section).
t1
F1
t6 t2
F2
t3 t4 t5
05757-002
CF
Figure 2. Timing Diagram for Frequency Outputs
Rev. PrA | Page 5 of 27
ADE7752B ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter VDD to AGND VDD to DGND Analog Input Voltage to AGND VAP, VBP, VCP, VN, IAP, IAN, IBP, IBN, ICP, and ICN Reference Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature 28-Lead SOIC, Power Dissipation JA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Rating -0.3 V to +7 V -0.3 V to +7 V -6 V to +6 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -40C to +85C -65C to +150C 150C 63 mW 55C/W 215C 220C
Preliminary Technical Data
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrA | Page 6 of 27
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CF
1 24 23 22 21
ADE7752B
F1 F2 S1 S0 CLKOUT
DGND 2 VDD REVP
3 4
IAP 5 IAN 6
ADE7752B
20 19
CLKIN TOP VIEW IBP 7 (Not to Scale) 18 SCF
17 16 15 14 13
IBN 8 ICP 9 ICN 10 AGND 11 REFIN/OUT 12
ABS VAP VBP VCP VN
05905-004
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 Mnemonic CF DGND Description Calibration Frequency Logic Output. The CF logic output gives instantaneous active power information. This output is intended to be used for calibration purposes. This provides the ground reference for the digital circuitry in the ADE7752B, that is, multiplier, filters, and digital-to-frequency converter. Because the digital return currents in the ADE7752B are small, it is acceptable to connect this pin to the analog ground plane of the whole system. Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7752B. The supply voltage should be maintained at 5 V 5% for specified operation. This pin should be decoupled to DGND with a 10 F capacitor in parallel with a 100 nF ceramic capacitor. This logic output goes logic high when negative power is detected on the sum of the three phase powers. This output is not latched and resets when positive power is once again detected (see the Negative Power Information section). Analog Inputs for Current Channels. These channels are intended for use with current transducers and are referenced in this document as current channels. These inputs are fully differential voltage inputs with maximum differential input signal levels of 0.5 V (see the Analog Inputs section). Both inputs have internal ESD protection circuitry; in addition, an overvoltage of 6 V can be sustained on these inputs without risk of permanent damage. This pin provides the ground reference for the analog circuitry in the ADE7752B (ADCs and reference). This pin should be tied to the analog ground plane or the quietest ground reference in the system. This quiet ground reference should be used for all analog circuitry, such as, anti-aliasing filters and current and voltage transducers. To keep ground noise around the ADE7752B to a minimum, the quiet ground plane should only connect to the digital ground plane at one point. It is acceptable to place the entire device on the analog ground plane. This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 2.4 V 8% and a typical temperature coefficient of 25 ppm/C. An external reference source can also be connected at this pin. In either case, this pin should be decoupled to AGND with a 1 F ceramic capacitor. Analog Inputs for the Voltage Channels. These channels are intended for use with voltage transducers and are referenced in this document as voltage channels. These inputs are single-ended voltage inputs with a maximum signal level of 0.5 V with respect to VN for specified operation. All inputs have internal ESD protection circuitry; in addition, an overvoltage of 6 V can be sustained on these inputs without risk of permanent damage. This logic input is used to select the method by which the three active energies from each phase are summed. It selects between the arithmetical sum of the three energies (ABS logic high) or the sum of the absolute values (ABS logic low). See the Mode Selection of the Sum of the Three Active Energies section. Select Calibration Frequency. This logic input is used to select the frequency on the calibration output CF. Table 7 shows how the calibration frequencies are selected. Master Clock for the ADCs and Digital Signal Processing. An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7752B. The clock frequency for the specified operation is 10 MHz. Ceramic load capacitors between 22 pF and 33 pF should be used with the gate oscillator circuit. Refer to the crystal manufacturer's data sheet for the load capacitance requirements.
Rev. PrA | Page 7 of 27
3
VDD
4
REVP
5, 6; 7, 8; 9, 10
IAP, IAN; IBP, IBN; ICP, ICN
11
AGND
12
REFIN/OUT
13, 14, 15, 16
VN, VCP, VBP, VAP
17
ABS
18 19
SCF CLKIN
ADE7752B
Pin No. 20 Mnemonic CLKOUT
Preliminary Technical Data
Description A crystal can be connected across this pin and CLKIN as described previously to provide a clock source for the ADE7752B. The CLKOUT pin can drive one CMOS load when an external clock is supplied at CLKIN or when a crystal is being used. These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conversion for design flexibility. Low Frequency Logic Outputs. F1 and F2 supply average active power information. The logic outputs can be used to drive electromechanical counters and 2-phase stepper motors directly (see the Transfer Function section).
21, 22 23, 24
S0, S1 F2, F1
Rev. PrA | Page 8 of 27
Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS
ADE7752B
Figure 4. Error as a Percent of Reading with Internal Reference (Wye Connection)
Figure 7. Error as a Percent of Reading over Temperature with Internal Reference (Wye Connection)
Figure 5. Error as a Percent of Reading over Power Factor with Internal Reference (Wye Connection)
Figure 8. Error as a Percent of Reading over Power Factor with Internal Reference (Delta Connection)
Figure 6. Error as a Percent of Reading over Power Factor with External Reference (Wye Connection)
Figure 9. Error as a Percent of Reading over Temperature with External Reference (Wye Connection)
Rev. PrA | Page 9 of 27
ADE7752B
Preliminary Technical Data
Figure 10. Error as a Percent of Reading over Frequency with an Internal Reference (Wye Connection)
Figure 12. Channel 1 Offset Distribution
Figure 11. Error as a Percent of Reading over Power Supply with External Reference (Wye Connection)
Figure 13. Error as a Percent of Reading over Power Supply with Internal Reference (Wye Connection)
Rev. PrA | Page 10 of 27
Preliminary Technical Data TERMINOLOGY
Measurement Error The error associated with the energy measurement made by the ADE7752B is defined by the following formula:
Energy Registered by ADE7762 - True Energy Percentage Error = x 100% True Energy
ADE7752B
ADC Offset Error This refers to the dc offset associated with the analog inputs to the ADCs. It means that with the analog inputs connected to AGND, the ADCs still see an analog input signal offset. However, because the HPF is always present, the offset is removed from the current channel and the power calculation is not affected by this offset. Gain Error The gain error of the ADE7752B is defined as the difference between the measured output frequency (minus the offset) and the ideal output frequency. The difference is expressed as a percentage of the ideal frequency. The ideal frequency is obtained from the ADE7752B transfer function (see the Transfer Function section).
Error between Channels The high-pass filter (HPF) in the current channel has a phase lead response. To offset this phase response and equalize the phase response between channels, a phase correction network is placed in the current channel. The phase correction network ensures a phase match between the current channels and voltage channels to within 0.1 over a range of 45 Hz to 65 Hz and 0.2 over a range of 40 Hz to 1 kHz (see Figure 25 and Figure 26). Power Supply Rejection (PSR) This quantifies the ADE7752B measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at a nominal supply (5 V) is taken. A 200 mV rms/100 Hz signal is then introduced onto the supply and a second reading is obtained under the same input signal levels. Any error introduced is expressed as a percentage of reading. See definition for Measurement Error. For the dc PSR measurement, a reading at nominal supplies (5 V) is taken. The supply is then varied 5% and a second reading is obtained with the same input signal levels. Any error introduced is again expressed as a percentage of reading.
Rev. PrA | Page 11 of 27
ADE7752B TEST CIRCUIT
VDD 10F ILOAD 1k RB 33nF 1k
6
Preliminary Technical Data
100nF
3 17
VDD 5 IAP
ABS F1 24 F2 23 825 CF 1 22pF CLKOUT 20 10MHz CLKIN 19 22pF S0 21 S1 22 SCF 18 1k VDD PS2501-1
K7 TO FREQ. COUNTER K8
ADE7752B
IAN IBP IBN ICP ICN VAP VBP VCP REFIN/OUT 12
33nF SAME AS IAP, IAN
7 8 9 10 16
SAME AS IAP, IAN 1M 220V 1k 33nF SAME AS VAP SAME AS VAP
15 14
100nF
10F
REVP 4 NOT CONNECTED VN AGND DGND
13 11 2
05905-015
1k 33nF
Figure 14. Test Circuit for Performance Curves
Rev. PrA | Page 12 of 27
Preliminary Technical Data THEORY OF OPERATION
The six signals from the current and voltage transducers are digitized with ADCs. These ADCs are 16-bit second-order - with an oversampling rate of 833 kHz. This analog input structure greatly simplifies transducer interface by providing a wide dynamic range and bipolar input for direct connection to the transducer. High-pass filters in the current channels remove the dc component from the current signals. This eliminates any inaccuracies in the active power calculation due to offsets in the voltage or current signals (see the HPF and Offset Effects section). The active power calculation is derived from the instantaneous power signal. The instantaneous power signal is generated by a direct multiplication of the current and voltage signals of each phase. In order to extract the active power component, the dc component, the instantaneous power signal is low-pass filtered on each phase. Figure 15 illustrates the instantaneous active power signal and shows how the active power information can be extracted by low-pass filtering the instantaneous power signal. This method is used to extract the active power information on each phase of the polyphase system. The total active power information is then obtained by adding the individual phase active power. This scheme correctly calculates active power for nonsinusoidal current and voltage waveforms at all power factors. All signal processing is carried out in the digital domain for superior stability over temperature and time.
p(t) = i(t) x v(t) WHERE: v(t) = V x cos (t) i(t) = I x cos (t) p(t) = V x I {1+ cos (2t)} 2 TIME INSTANTANEOUS POWER SIGNAL - p(t)
ADE7752B
The low frequency output of the ADE7752B is generated by accumulating the total active power information. This low frequency inherently means a long accumulation time between output pulses. The output frequency is therefore proportional to the average active power. This average active power information can, in turn, be accumulated (for example, by a counter) to generate active energy information. Because of its high output frequency and therefore shorter integration time, the CF output is proportional to the instantaneous active power. This pulse is useful for system calibration purposes that would take place under steady load conditions.
POWER FACTOR CONSIDERATIONS
Low-pass filtering, the method used to extract the active power information from the individual instantaneous power signal, is still valid when the voltage and current signals of each phase are not in phase. Figure 16 displays the unity power factor condition and a displacement power factor (DPF) = 0.5, that is, current signal lagging the voltage by 60, for one phase of the polyphase. Assuming that the voltage and current waveforms are sinusoidal, the active power component of the instantaneous power signal (the dc term) is given by
V x 1 x cos(60) 2
(1)
VxI VxI 2
VxI 2
INSTANTANEOUS VA x IA + VB x IB + ACTIVE POWER SIGNAL VC x IC 2
HPF IAP IAN ADC MUL TIPLIER VAP ADC HPF IBP IBN ADC MUL TIPLIER VBP ADC HPF ICP ICN ADC MUL TIPLIER VCP VN ADC LPF LPF
ABS INSTANTANEOUS TOTAL POWER SIGNAL
|X|
DIGITAL-TOFREQUENCY LPF |X| DIGITAL-TOFREQUENCY CF F1 F2
|X|
05757-016
Figure 15. Signal Processing Block Diagram
Rev. PrA | Page 13 of 27
ADE7752B
This is the correct active power calculation.
INSTANTANEOUS POWER SIGNAL INSTANTANEOUS ACTIVE POWER SIGNAL
Preliminary Technical Data
i (t ) = I O + 2 x
n=0
V I x sin (nt )
n n
(3)
Vx I 2
0V CURRENT VOLTAGE INSTANTANEOUS POWER SIGNAL INSTANTANEOUS ACTIVE POWER SIGNAL
where: i(t) is the instantaneous current. IO is the dc component. In is the rms value of current harmonic n. n is the phase angle of the current harmonic. Using Equations 2 and 3, the active power, P, can be expressed in terms of its fundamental active power (P1) and harmonic active power (PH). P = P1 + PH
Vx I x cos(60) 2 0V
05757-017
where:
P = V 1 x I1 cos 1 1
VOLTAGE 60
1 = 1 - 1
PH =
(4)
CURRENT
Figure 16. DC Component of Instantaneous Power Signal
V
n =1
n
x I n cos n
(5)
NONSINUSOIDAL VOLTAGE AND CURRENT
The active power calculation method also holds true for nonsinusoidal current and voltage waveforms. All voltage and current waveforms in practical applications have some harmonic content. Using the Fourier Transform, instantaneous voltage and current waveforms can be expressed in terms of their harmonic content
v (t ) = Vo + 2 x
n = n - n As can be seen from Equation 5, a harmonic active power component is generated for every harmonic, provided that harmonic is present in both the voltage and current waveforms. The power factor calculation has been shown to be accurate in the case of a pure sinusoid. Therefore, the harmonic active power also correctly accounts for power factor since harmonics are made up of a series of pure sinusoids. A limiting factor on harmonic measurement is the bandwidth. On the ADE7752B, the bandwidth of the active power measurement is 14 kHz with a master clock frequency of 10 MHz.
n=0
V
n
x sin (nt + n )
(2)
where: v(t) is the instantaneous voltage. VO is the average value. Vn is the rms value of voltage harmonic n. and n is the phase angle of the voltage harmonic.
Rev. PrA | Page 14 of 27
Preliminary Technical Data ANALOG INPUTS
CURRENT CHANNELS
The voltage outputs from the current transducers are connected to the ADE7752B current channels, which are fully differential voltage inputs. IAP, IBP, and ICP are the positive inputs for IAN, IBN, and ICN, respectively. The maximum peak differential signal on the current channel should be less than 500 mV (353 mV rms for a pure sinusoidal signal) for the specified operation.
IAP-IAN +500mV IAP DIFFERENTIAL INPUT 500mV MAX PEAK VCM COMMON-MODE 25mV MAX -500mV VCM
05757-018
ADE7752B
VOLTAGE CHANNELS
The output of the line voltage transducer is connected to the ADE7752B at this analog input. Voltage channels are a pseudodifferential voltage input. VAP, VBP, and VCP are the positive inputs with respect to VN. The maximum peak differential signal on the voltage channel is 500 mV (353 mV rms for a pure sinusoidal signal) for specified operation. Figure 18 illustrates the maximum signal levels that can be connected to the ADE7752B voltage channels.
VAP-VN
IA
IAN
+500mV VAP DIFFERENTIAL INPUT 500mV MAX PEAK VCM COMMON-MODE 25mV MAX -500mV VCM
05757-019
AGND
VA
VN
Figure 17. Maximum Signal Levels, Current Channel
AGND
The maximum signal levels on IAP and IAN are shown in Figure 17. The maximum differential voltage between IAP and IAN is 500 mV. The differential voltage signal on the inputs must be referenced to a common mode, for example, AGND. The maximum common-mode signal shown in Figure 17 is 25 mV.
Figure 18. Maximum Signal Levels, Voltage Channel
Voltage channels must be driven from a common-mode voltage, that is, the differential voltage signal on the input must be referenced to a common mode (usually AGND). The analog inputs of the ADE7752B can be driven with common-mode voltages of up to 25 mV with respect to AGND. However, best results are achieved using a common mode equal to AGND.
Rev. PrA | Page 15 of 27
ADE7752B TYPICAL CONNECTION DIAGRAMS
CURRENT CHANNEL CONNECTION
Figure 19 shows a typical connection diagram for the current channel (IA). A current transformer (CT) is the current transducer selected for this example. Notice the common-mode voltage for the current channel is AGND and is derived by center tapping the burden resistor to AGND. This provides the complementary analog input signals for IAP and IAN. The CT turns ratio and burden resistor Rb are selected to give a peak differential voltage of 500 mV at maximum load. In theory it is better to center tap Rb; however, this requires very careful attention to the layout and matching of the resistors to ensure that the channels have the same resistance. A single resistor may be more practical and is a valid design choice.
CT Rb Rf Cf 500mV IAP IAN
Preliminary Technical Data
METER CONNECTIONS
In 3-phase service, two main power distribution services exist: 3-phase 4-wire or 3-phase 3-wire. The additional wire in the 3-phase 4-wire arrangement is the neutral wire. The voltage lines have a phase difference of 120 (2/3 radians) between each other (see Equation 6).
V A (t ) = 2 x V A x cos ( l t ) 2 V B (t ) = 2 x V B x cos l t + 3 4 V C (t ) = 2 x VC x cos l t + 3 where VA, VB, and VC represent the voltage rms values of the different phases. The current inputs are represented by
I A (t ) = 2 I A x cos ( l t + A ) I B (t ) = 2 I B x cos l t + I C (t ) = 2 I C x cos l t + where: IA, IB, and IC represent the rms value of the current of each phase. A, B, and C represent the phase difference of the current and voltage channel of each phase. The instantaneous powers can then be calculated as follows: PA(t) = VA(t) x IA(t) PB(t) = VB(t) x IB(t) PC(t) = VC(t) x IC(t) Then:
PA (t ) = VA x I A x cos( A ) - VA x I A x cos (2lt + A )
(6)
PHASE NEUTRAL
Figure 19. Typical Connection for Current Channels
VOLTAGE CHANNELS CONNECTION
Figure 20 shows two typical connections for the voltage channel. The first option uses a potential transformer (PT) to provide complete isolation from the main voltage. In the second option, the ADE7752B is biased around the neutral wire, and a resistor divider is used to provide a voltage signal proportional to the line voltage. Adjusting the ratio of Ra, Rb, and VR is a convenient way of carrying out a gain calibration on the meter. VR can be implemented using either a potentiometer or a binary weighted series of resistors. Either configuration works, however, the potentiometer is subject to noise over time. Two fixed value resistors can be used in place of VR to minimize the noise.
PT 500mV Rf AGND PHASE NEUTRAL Cf Cf Rf Cf VAP VN
05757-020
IP
Rf
Cf
2 + B 3 4 + C 3
(7)
4 PB (t ) = VB x I B x cos(B ) - VB x I B x cos 2lt + + B 3 2 t + 8 + PC (t ) = VC x IC x cos(C ) - VC x IC x cos l C 3
(8)
Ra* Rb* VR*
500mV Rf Cf
VAP VN
05757-021
As shown in Equation 8, in the ADE7752B, the active power calculation per phase is made when current and voltage inputs of one phase are connected to the same channel (A, B, or C). Then the summation of each individual active power calculation gives the total active power information, P(t) = PA(t) + PB(t) + PC(t).
PHASE NEUTRAL
* Ra >> Rf + VR; * Rb + VR = Rf
Figure 20. Typical Connections for Voltage Channels
Rev. PrA | Page 16 of 27
Preliminary Technical Data
Figure 21 shows the connections of the ADE7752B analog inputs with the power lines in a 3-phase 3-wire delta service.
Ra* Rb* VR* Rb* CT PHASE A
PHASE A
ADE7752B
Figure 22 shows the connections of the ADE7752B analog inputs with the power lines in a 3-phase 4-wire Wye service.
Ra* Rb* Cf
Cf
VAP IAP IAN ANTIALIASING FILTERS
VR* Rb* CT ANTIALIASING FILTERS CT
VAP IAP IAN
PHASE C SOURCE Rf CT PHASE B ANTIALIASING FILTERS IBP IBN VBP
05757-022
SOURCE
PHASE B
Ra* Rb*
Cf Rb*
ANTIALIASING FILTERS IBP IBN VBP
VN Cf
LOAD
PHASE C
VR* CT
Ra* Rb* VR*
Cf
Rb*
Ra* Rb* VR* Rf
Cf Rb*
ANTIALIASING FILTERS ICP ICN VCP LOAD
* Ra >> Rf + VR; * Rb + VR = Rf
Figure 21. 3-Phase 3-Wire Meter Connection with ADE7752B
CF
* Ra >> Rf + VR; * Rb + VR = Rf
Figure 22. 3-Phase 4-Wire Meter Connection with ADE7752B
Note that only two current inputs and two voltage inputs of the ADE7752B are used in this case. The active power calculated by the ADE7752B does not depend on the selected channels.
Rev. PrA | Page 17 of 27
05757-023
VN
ADE7752B POWER SUPPLY MONITOR
The ADE7752B contains an on-chip power supply monitor. The power supply (VDD) is monitored continuously by the ADE7752B. At power up, when the supply is less than 4V 2% and VREF is less than 1.9 V (typ), the outputs of the ADE7752B are inactive and the data path is held in reset. Once VDD is greater than 4V 2% and VREF is greater than 1.9 V (typ), the chip is active and energy accumulation begins. At power-down, when VDD falls below 4 V or VREF falls below 1.9 V (typ), the data path is again held in reset. This implementation ensures correct device operation at powerup and at power-down. The power supply monitor has built-in hysteresis and filtering. This gives a high degree of immunity to false triggering due to noisy supplies. The power supply and decoupling for the part should be such that the ripple at VDD does not exceed 5% as specified for normal operation.
5V 4V
Preliminary Technical Data
VDD
2.4V 1.9V
VREF
0V
INTERNAL INACTIVE RESET
ACTIVE
INACTIVE
Figure 23. On-Chip Power Supply Monitor
Rev. PrA | Page 18 of 27
05757-024
ADE7752B HPF AND OFFSET EFFECTS
Figure 24 shows the effect of offsets on the active power calculation. An offset on the current channel and voltage channel contributes a dc component after multiplication as shown in Figure 24. Since this dc component is extracted by the LPF and is used to generate the active power information for each phase, the offsets can contribute a constant error to the total active power calculation. The HPF in the current channels avoids this problem easily. By removing the offset from at least one channel, no error component can be generated at dc by the multiplication. Error terms at cos(t) are removed by the LPF and the digital-to-frequency conversion (see the Digital-toFrequency Conversion) section.
Preliminary Technical Data
The ADE7752B is phase compensated up to 1 kHz as shown. This ensures correct active harmonic power calculation even at low power factors.
{V cos(t ) + VOS }x {I cos(t ) + I OS } =
+ VOS x I OS + VOS x I cos(t ) + I OS x V cos(t ) (9) 2 V xI + x cos(2t ) 2
V xI
Figure 25. Phase Error between Channels (0 Hz to 1 kHz)
VOS x IOS Vx I 2
DC COMPONENT (INCLUDING ERROR TERM) IS EXTRACTED BY THE LPF FOR REAL POWER CALCULA TION
IOS x V
05757-026
VOS x I 0 2 FREQUENCY - RAD/S
Figure 24. Effect of Channel Offset on the Active Power Calculation
The HPF in the current channels has an associated phase response that is compensated for on-chip. Figure 25 and Figure 26 show the phase error between channels with the compensation network.
Figure 26. Phase Error Between Channels (40 Hz to 70 Hz)
Rev. PrA | Page 19 of 27
ADE7752B DIGITAL-TO-FREQUENCY CONVERSION
After multiplication, the digital output of the low-pass filter contains the active power information of each phase. However, since this LPF is not an ideal brick wall filter implementation, the output signal also contains attenuated components at the line frequency and its harmonics, that is, cos(ht), where h = 1, 2, 3 .... The magnitude response of the filter is given by
Preliminary Technical Data
The average value of a sinusoidal signal is zero. Thus, the frequency generated by the ADE7752B is proportional to the average active power. Figure 27 shows the digital-to-frequency conversion for steady load conditions, that is, constant voltage and current. The frequency output CF varies over time, even under steady load conditions (see Figure 27). This frequency variation is primarily due to the cos(2t) components in the instantaneous active power signal. The output frequency on CF can be up to 160x higher than the frequency on F1 and F2. The higher output frequency is generated by accumulating the instantaneous active power signal over a much shorter time, while converting it to a frequency. This shorter accumulation period means less averaging of the cos(2t) component. Therefore, some of this instantaneous power signal passes through the digital-to-frequency conversion. Where CF is used for calibration purposes, the frequency counter should average the frequency to remove the ripple and obtain a stable frequency. If CF is being used to measure energy, for example, in a microprocessor-based application, the CF output should also be averaged to calculate power. Because the outputs F1 and F2 operate at a much lower frequency, significant averaging of the instantaneous active power signal is carried out. The result is a greatly attenuated sinusoidal content and a virtually ripple-free frequency output on F1 and F2, which are used to measure energy in a stepper-motor based meter.
|H ( f )| =
1 f 1+ 8
2
(10)
where the -3 dB cutoff frequency of the low-pass filter is 8 Hz. For a line frequency of 50 Hz, this would give an attenuation of the 2(100 Hz) component of approximately -22 dB. The dominating harmonic is twice the line frequency, that is, cos(2t), due to the instantaneous power signal. Figure 27 shows the instantaneous active power signal at the output of the CF, which still contains a significant amount of instantaneous power information, cos(2t). This signal is then passed to the digital-to-frequency converter where it is integrated (accumulated) over time to produce an output frequency. This accumulation of the signal suppresses or averages out any non-dc component in the instantaneous active power signal.
VA LPF MULTIPLIER IA
ABS
|X|
F1 DIGITAL-TOFREQUENCY
VB LPF MULTIPLIER IB |X|
F1 F2 DIGITAL-TOFREQUENCY
FREQUENCY
TIME CF CF
VC LPF MULTIPLIER IC LPF TO EXTRACT REAL POWER (DC TERM) |X| Vx I 2
FREQUENCY
TIME
cos(2t) ATTENUATED BY LPF
0
2
05757-029
FREQUENCY - RAD/S INSTANTANEOUS REAL POWER SIGNAL (FREQUENCY DOMAIN)
Figure 27. Active Power-to-Frequency Conversion
Rev. PrA | Page 20 of 27
Preliminary Technical Data
POWER MEASUREMENT CONSIDERATIONS
Calculating and displaying power information always have some associated ripple that depends on the integration period used in the MCU to determine average power as well as the load. For example, at light loads, the output frequency can be 10 Hz. With an integration period of two seconds, only about 20 pulses are counted. The possibility of missing one pulse always exists since the ADE7752B output frequency is running asynchronously to the MCU timer. This would result in a 1-in-20 or 5% error in the power measurement. To remedy this, an appropriate integration time should be considered to achieve the desired accuracy.
ADE7752B
MODE SELECTION OF THE SUM OF THE THREE ACTIVE ENERGIES
The ADE7752B can be configured to execute the arithmetic sum of the three active energies, Wh = WhA + WhB + WhC, or the sum of the absolute value of these energies, Wh = |WhA| + |WhB| + |WhC|. The selection between the two modes can be made by setting the ABS pin. Logic high and logic low applied on the ABS pin correspond to the arithmetic sum and the sum of absolute values, respectively. When the sum of the absolute values is selected, the active energy from each phase is always counted positive in the total active energy. It is particularly useful in 3-phase 4-wire instillation where the sign of the active power should always be the same. If the meter is misconnected to the power lines, that is, CT connected in the wrong direction then the total active energy recorded without this solution can be reduced by twothirds. The sum of the absolute values assures that the active energy recorded represents the actual active energy delivered. Regardless of the mode selected using this pin, the reverse power pin still detects when negative power is present on the sum of the three phase inputs.
Rev. PrA | Page 21 of 27
ADE7752B TRANSFER FUNCTION
FREQUENCY OUTPUTS F1 AND F2
The ADE7752B calculates the product of six voltage signals (on current channel and voltage channel) and then low-pass filters this product to extract active power information. This active power information is then converted to a frequency. The frequency information is output on F1 and F2 in the form of active high pulses. The pulse rate at these outputs is relatively low, for example, 2.01 Hz maximum for ac signals with SCF = S0 = 0; S1 = 1 (see Table 6). This means that the frequency at these outputs is generated from active power information accumulated over a relatively long period. The result is an output frequency that is proportional to the average active power. The averaging of the active power signal is implicit to the digital-to-frequency conversion. The output frequency or pulse rate is related to the input voltage signals by the following equation:
Freq = 6.181 x (VAN x I A + VBN x I B + VCN x IC ) x F 1- 7 VREF 2
Preliminary Technical Data
Example 1
Thus, if full-scale differential dc voltages of +500 mV are applied to VA, VB, VC, IA, IB, and IC, respectively (500 mV is the maximum differential voltage that can be connected to current and voltage channels), then the expected output frequency is calculated as follows: F1-7 = 0.58 Hz, SCF = S0 = S1 = 1 VAN = VBN = VCN = IA = IB = IC = 500 mV dc = 0.5 V(rms of dc = dc) VREF = 2.4 V (nominal reference value) Note that if the on-chip reference is used, actual output frequencies can vary from device to device due to reference tolerance of 8%.
Freq = 3 x 6.181 x 0.5 x 0.5 x 0.58 2.4 2 = 0.467 Hz
(12)
(11)
Example 2
In this example, with ac voltages of 500 mV peak applied to the voltage channels and current channels, the expected output frequency is calculated as follows:
F1- 7 = 0.58 Hz, SCF = S0 = S1 = 1 VAN = VBN = VCN = IA = IB = IC 2 VREF = 2.4 V (nominal reference value) = 500 mV peak AC = 0.5 Vrms
where: Freq = output frequency on F1 and F2 (Hz). VAN, VBN, and VCN = differential rms voltage signal on voltage channels (V). IA, IB, and IC = differential rms voltage signal on current channels (V). VREF = the reference voltage (2.4 V 8%) (V). F1-7 = one of seven possible frequencies selected by using the logic inputs SCF, S0, and S1 (see Table 5).
Table 5. F1-7 Frequency Selection1
SCF 0 1 0 1 0 1 0 1
1
(13)
Note that if the on-chip reference is used, actual output frequencies can vary from device to device due to reference tolerance of 8%.
Freq = 3 x 6.181 x 0.5 x 0.5 x 0.58 2 x 2 x 2.4 2 = 0.233 Hz
S1 0 0 0 0 1 1 1 1
S0 0 0 1 1 0 0 1 1
F1-7 (Hz) 2.30 4.61 1.15 4.61 5.22 1.15 0.58 0.58
(14)
F1-7 is a fraction of the master clock and therefore varies if the specified CLKIN frequency is altered.
As can be seen from these two example calculations, the maximum output frequency for ac inputs is always half of that for dc input signals. The maximum frequency also depends on the number of phases connected to the ADE7752B. In a 3-phase 3-wire delta service, the maximum output frequency is different from the maximum output frequency in a 3-phase 4-wire Wye service. The reason is that there are only two phases connected to the analog inputs, but also that in a delta service, the current channel input and voltage channel input of the same phase are not in phase in normal operation.
Rev. PrA | Page 22 of 27
Preliminary Technical Data
Example 3
In this example, the ADE7752B is connected to a 3-phase 3wire delta service as shown in Figure 21. The total active energy calculation processed in the ADE7752B can be expressed as Total Active Power = (VA - VC) x IA + (VB - VC) x IB where: VA, VB, and VC represent the voltage on phase A, phase B, and phase C, respectively. IA and IB represent the current on phase A and phase B, respectively. As the voltage and current inputs respect Equations 5 and 6, the total active power (P) is
P = (VA - VC )
ADE7752B
Note that if the on-chip reference is used, actual output frequencies can vary from device to device due to reference tolerance of 8%.
Freq = 2 x 6.181 x 0.5 x 0.5 x 0.60 2 x 2 x 2.4 2 x 3 = 0.139 Hz 2
(20)
Table 6 shows a complete listing of all maximum output frequencies when using all three channel inputs.
Table 6: Maximum Output Frequency on F1 and F2
Maximum Frequency for AC Inputs (Hz) 0.93 1.86 0.46 1.86 2.10 0.46 0.23 0.23 Maximum Frequency for DC Inputs (Hz) 1.85 3.71 0.93 3.71 4.20 0.93 0.47 0.47
SCF 0 1 0 1 0 1 0 1
S1 0 0 0 0 1 1 1 1
S0 0 1 1 1 0 0 1 1
(IAP - IAN ) + (VB - VC ) x (IBP - IBN )
(15)
4 P = 2 x V A x cos(l t ) - 2 x VC x cos l t + 3 x 2 x I A x cos(l t ) 2 4 + 2 x V B x cos l t + - v 2 x VC x cos l t + 3 3 2 x 2 x I B x cos l t + 3
FREQUENCY OUTPUT CF
The pulse output calibration frequency (CF) is intended for use during calibration. The output pulse rate on CF can be up to 64x the pulse rate on F1 and F2. Table 7 shows how the two frequencies are related, depending on the states of the logic inputs S0, S1, and SCF. Because of its relatively high pulse rate, the frequency at this logic output is proportional to the instantaneous active power. As is the case with F1 and F2, the frequency is derived from the output of the low-pass filter after multiplication. However, since the output frequency is high, this active power information is accumulated over a much shorter time. Thus, less averaging is carried out in the digital-tofrequency conversion. The CF output is much more responsive to power fluctuations with much less averaging of the active power signal (see Figure 15).
Table 7. Maximum Output Frequency on CF
SCF 0 1 0 1 0 1 0 1 S1 0 0 0 0 1 1 1 1 S0 0 0 1 1 0 0 1 1 F1-7 (Hz) 2.3 4.61 1.15 4.61 5.22 1.15 0.58 0.58 CF Maximum for AC Signals (Hz) 16 x F1, F2 = 14.88 8 x F1, F2 = 14.88 32 x F1, F2 = 14.88 16 x F1, F2 = 29.76 160 x F1, F2 = 336 16 x F1, F2 = 7.36 32 x F1, F2 = 7.36 16 x F1, F2 = 3.68
For simplification, assume that A = B = C = 0 and VA = VB = VC = V. The preceding equation becomes
2 2 P = 2 x V x I A x sin x sin l t + x cos( l t ) 3 3 2 + 2 x V x I B x sin x sin( l t + )x cos l t + 3 3
(16)
P then becomes
2 2 P = VAN x I A x sin + sin 2 l t + 3 3 + VBN x I B x sin + sin 2 l t + 3 3
(17)
where: VAN = V x sin(2/3). VBN = V x sin(/3). As the LPF on each channel eliminates the 2l component of the equation, the active power measured by the ADE7752B is P = V AN x I A x 3 3 + V BN x I B x 2 2 (18)
If full-scale ac voltage of 500 mV peak is applied to the voltage channels and current channels, the expected output frequency is calculated as follows:
F1- 7 = 0.60Hz, SCF = S0 = S1 = 1 VAN = VBN = IA = IB = IC = 500 mV peak ac = VCN = IC = 0 VREF = 2.4V nominal reference value 0.5 2 V rms
(19)
Rev. PrA | Page 23 of 27
Preliminary Technical Data SELECTING A FREQUENCY FOR AN ENERGY METER APPLICATION
As shown in Table 5, the user can select one of seven frequencies. This frequency selection determines the maximum frequency on F1 and F2. These outputs are intended to be used to drive the energy register (electromechanical or other). Since seven different output frequencies can be selected, the available frequency selection has been optimized for a 3-phase 4-wire service with a meter constant of 100 imp/kWhr and a maximum current of between 10 A and 100 A. Table 8 shows the output frequency for several maximum currents (IMAX) with a line voltage of 220 V (phase neutral). In all cases, the meter constant is 100 imp/kWhr.
Table 8. F1 and F2 Frequency at 100 imp/kWhr
IMAX (A) 10 25 40 60 80 100 F1 and F2 (Hz) 0.18 0.46 0.73 1.10 1.47 1.83
ADE7752B
When selecting a suitable F1-7 frequency for a meter design, the frequency output at IMAX (maximum load) with a 100 imp/kWhr meter constant should be compared with Column 5 of Table 9. The frequency that is closest in Table 9 determines the best choice of frequency (F1-7). For example, if a 3-phase 4-wire Wye meter with a 25 A maximum current is being designed, the output frequency on F1 and F2 with a 100 imp/kWhr meter constant is 0.46 Hz at 25 A and 220 V (see Table 8). Looking at Table 9, the closest frequency to 0.46 Hz in Column 5 is 0.53 Hz. Therefore, F1-7 = 5.22 Hz is selected for this design.
FREQUENCY OUTPUTS
Figure 2 shows a timing diagram for the various frequency outputs. The outputs F1 and F2 are the low frequency outputs that can be used to directly drive a stepper motor or electromechanical impulse counter. The F1 and F2 outputs provide two alternating high going pulses. The pulse width (t1) is set at 120 ms, and the time between the rising edges of F1 and F2 (t3) is approximately half the period of F1 (t2). If, however, the period of F1 and F2 falls below 550 ms (1.81 Hz), the pulse width of F1 and F2 is set to half of their period. The maximum output frequencies for F1 and F2 are shown in Table 6. The high frequency CF output is intended to be used for communications and calibration purposes. CF produces a 90 mswide active high pulse (t4) at a frequency proportional to active power. The CF output frequencies are given in Table 7. As in the case of F1 and F2, if the period of CF (t5) falls below 190 ms, the CF pulse width is set to half the period. For example, if the CF frequency is 20 Hz, the CF pulse width is 25 ms.
The F1-7 frequencies allow complete coverage of this range of output frequencies on F1 and F2. When designing an energy meter, the nominal design voltage on the voltage channels should be set to half scale to allow for calibration of the meter constant. The current channel should also be no more than half scale when the meter sees maximum load. This allows overcurrent signals and signals with high crest factors to be accommodated. Table 9 shows the output frequency on F1 and F2 when all six analog inputs are half scale.
Table 9. F1 and F2 Frequency with Half-Scale AC Inputs
SCF 0 1 0 1 0 1 0 1 S1 0 0 0 0 1 1 1 1 S0 0 0 1 1 0 0 1 1 F1-7 (Hz) 2.3 4.61 1.15 4.61 5.22 1.15 0.58 0.58 Frequency on F1 and F2 (Half-Scale AC Inputs) (Hz) 0.23 0.46 0.12 0.46 0.53 0.12 0.06 0.06
NO LOAD THRESHOLD
The ADE7752B includes no load threshold and start-up current circuitry features that eliminate any creep effects in the meter. The circuit is designed to issue a minimum output frequency. Any load generating a frequency lower than this minimum output frequency does not cause a pulse to be issued on F1, F2, or CF. The no-load threshold is determined by the sum of all phases. The minimum output frequency is given as 0.0075% of the fullscale output frequency for each of the F1-7 frequency selections, or approximately 0.0029% of the F1-7 frequency (see Table 10). For example, for an energy meter with a 100 imp/kWhr meter constant using F1-7 (4.61 Hz), the minimum output frequency at F1 or F2 would be 13.35 x 10-5 Hz. This would be 2.13 x 10-3 Hz at CF (16 x F1 Hz). In this example, the no load threshold would be equivalent to 4.8 W of load or a start-up current of 20.03 mA at 240 V.
Rev. PrA | Page 24 of 27
Preliminary Technical Data
Table 10. CF, F1, and F2 Minimum Frequency at No Load Threshold
SCF 0 1 0 1 0 1 0 1 S1 0 0 0 0 1 1 1 1 S0 0 0 1 1 0 0 1 1 F1, F2 Minimum (Hz) 6.94E - 05 1.39E - 04 3.47E - 05 1.39E - 04 1.58E - 04 3.47E - 05 1.75E - 05 1.75E - 05 CF Minimum (Hz) 1.11E - 03 1.11E - 03 1.11E - 03 2.23E - 03 2.52E - 02 5.55E - 04 5.60E - 04 2.80E - 04
ADE7752B
NEGATIVE POWER INFORMATION
The ADE7752B detects when total power, calculated as the sum of the three phases, is negative. This mechanism can detect an incorrect connection of the meter or generation of negative active energy. The REVP pin output goes active high when negative power is detected on the sum of the three phase inputs. If positive active power is detected on the sum of three phases, then REVP pin output is low. The REVP pin output changes state at the same time as a pulse is issued on CF. If the sum of the phases measure negative power, then the REVP pin output stays high until the sum of the phases measures positive power.
Rev. PrA | Page 25 of 27
ADE7752B OUTLINE DIMENSIONS
15.60 (0.6142) 15.20 (0.5984)
24 13
Preliminary Technical Data
7.60 (0.2992) 7.40 (0.2913)
1 12
10.65 (0.4193) 10.00 (0.3937)
2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 1.27 (0.0500) BSC 0.10 0.51 (0.020) 0.31 (0.012) 8 SEATING 0.33 (0.0130) 0 PLANE 0.20 (0.0079)
0.75 (0.0295) x 45 0.25 (0.0098)
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013-AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 28. 24-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-24) Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model ADE7752BARWZ1 ADE7752BARWZ-RL1 ADE7752BARW ADE7752BARW-RL EVAL-ADE7752BEB
1 2
Package Description 28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Standard Small Outline Package [SOIC_W] ADE7752B Evaluation Board
Package Option RW-282 RW-28 on 13" Reels RW-28 RW-28 on 13" Reels
Z = Pb-free part. RW = small outline wide body package in tubes.
Rev. PrA | Page 26 of 27
Preliminary Technical Data NOTES
ADE7752B
(c) 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05905-0-1/06(PrA)
Rev. PrA | Page 27 of 27

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